Backside cavities for thermal tuning optimization of silicon ring resonators
Résumé
Silicon ring resonators on SOI substrates are well known and widely studied. They are commonly used in datacom and high-performance computing for wavelength multiplexing and spectral filters. They can be tuned to the desired frequency with resistive heaters, which is the primary power budget of the device. In this work, the impact of backside cavities etched in the bulk silicon of SOI substrates below ring resonators is studied. Simulations show that those backside cavities improve significantly heat confinement and minimizes heat losses usually due to conduction in the Si substrate. Backside cavities have been successfully etched in the bulk of the SOI substrate to improve heat trapping within the silicon rings. The etching process is compatible with the standard silicon photonics interposer process flow. Power consumption studies have been performed with a reference ring resonator on SOI and ring resonators with different backside cavity diameters. These results will be discussed with respect to the backside cavity opening. A 72% power consumption reduction for a 10 µm diameter ring resonator on SOI has been achieved with a backside opening of 100 µm deep and 40µm diameter. The cavities opening did not impact the optical ring performances.
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