Considerations for High-Speed Configurable- bandwidth Time-interleaved Digital Delta-Sigma Modulators and Synthesis in 28 nm UTBB FDSOI - Université de Lille Accéder directement au contenu
Communication Dans Un Congrès Année : 2015

Considerations for High-Speed Configurable- bandwidth Time-interleaved Digital Delta-Sigma Modulators and Synthesis in 28 nm UTBB FDSOI

Résumé

This paper presents the design and simulation of a time-interleaved delta-sigma modulator as part of a digital transmitter chain. The architecture is chosen based on a critical path analysis in order to reach very high frequency operation. The modulator's configurability allows it to target signal bandwidths from 20 MHz up to 160 MHz with a SNR greater than 67 dB. Finally, the modulator is synthesized using standard cells in 28nm FDSOI CMOS from STMicroelectronics and simulated for different numbers of time-interleaved channels, reaching a sample rate of up to 6 GS/s. An optimum number of channels can be found based on a trade-off between operating frequency, supply voltage, power consumption and area.
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Dates et versions

hal-02314236 , version 1 (11-10-2019)

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Razvan-Cristian Marin, Antoine Frappé, Andreas Kaiser, Andreia Cathelin. Considerations for High-Speed Configurable- bandwidth Time-interleaved Digital Delta-Sigma Modulators and Synthesis in 28 nm UTBB FDSOI. 2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS), Jun 2015, Grenoble, France. pp.1-4, ⟨10.1109/NEWCAS.2015.7182049⟩. ⟨hal-02314236⟩
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