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Article Dans Une Revue IEEE Solid-State Circuits Letters Année : 2020

A wide tuning range delay element for event-driven processing of low-frequency signals in 28-nm FD-SOI CMOS

Résumé

This paper presents a widely tunable digital delay element suitable for low-power low-frequency continuous-time digital signal processing systems. The design uses features of the 28 nm FD-SOI CMOS technology to precisely control currents in the pA range and significantly reduce leakage power. The measured tuning range is significantly larger than prior art covering more than 3 decades from 30 ns to 100 µs making it suitable for CT-DSP low frequency filters. At 0.7 V supply voltage, the dynamic power consumption is 15 fJ/event with a residual power consumption due to leakage of 14 pW.
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Dates et versions

hal-03041576 , version 1 (05-12-2020)

Identifiants

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Angel Gonzalez, Antoine Frappé, Benoit Larras, Andreas Kaiser, Philippe Cathelin. A wide tuning range delay element for event-driven processing of low-frequency signals in 28-nm FD-SOI CMOS. IEEE Solid-State Circuits Letters, 2020, 3, pp.198-201. ⟨10.1109/LSSC.2020.3010877⟩. ⟨hal-03041576⟩
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